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ltc3860 1 3860fc typical application description dual, multiphase step-down voltage mode dc/dc controller with current sharing the ltc ? 3860 is a dual, polyphase ? synchronous step- down switching regulator controller for high current distributed power systems, digital signal processors, and other telecom and industrial dc/dc power supplies. it uses a constant frequency voltage mode architecture combined with very low offset, high bandwidth error ampli? ers and a remote output sense differential ampli? er for excellent transient response and output regulation. the controller incorporates lossless inductor dcr current sensing to maintain current balance between phases and to provide overcurrent protection. the chip operates from a v cc supply between 3v and 5.5v and is designed for step- down conversion from v in between 3v and 24v to output voltages between 0.6v and v cc C 0.5v. the track/ss pins provide programmable soft-start or tracking functions. inductor current reversal is disabled during soft-start to safely power prebiased loads. the con- stant operating frequency can be synchronized to an exter- nal clock or linearly programmed from 250khz to 1.25mhz. up to six ltc3860 controllers can operate in parallel for 1-, 2-, 3-, 4-, 6- or 12-phase operation. the ltc3860 is available in a 32-pin 5mm 5mm qfn package. features applications n operates with power blocks, drmos or external gate drivers and mosfets n constant frequency voltage mode control with accurate current sharing n 0.75% 0.6v voltage reference n differential remote output voltage sense ampli? er n multiphase capabilityup to 12-phase operation n programmable current limit n safely powers a prebiased load n programmable or pll-synchronizable switching frequency up to 1.25mhz n lossless current sensing using inductor dcr or precision current sensing with sense resistor n v cc range: 3v to 5.5v n v in range: 3v to 24v n power good output voltage monitor n output voltage tracking capability n programmable soft-start n available in a 32- pin 5mm 5mm qfn package n high current distributed power systems n digital signal processor and asic supplies n telecom systems n industrial power supplies l , lt, ltc, ltm, polyphase, module, linear technology and the linear logo are registered trademarks and no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6144194, 5055767 vinsns v cc freq fb2 i lim2 fb1 comp1,2 ss1,2 in v logic v cc boost gnd tg ts bg run1,2 i lim1 isns1p isns1n isns2n isns2p ltc3860 pwm1 ltc4449 v in v in sw1 0.3h sgnd clkin vsnsout vsnsn vsnsp pwm2 pwm2 pwm1 470f 1f 0.22f 0.22f tg1 bg1 v cc v cc 0.22f 100pf 1nf 0.1f 220pf 12.7k 220 50k 2.32k 2.32k 20k 20k 33pf v out v in v cc in v logic v cc boost gnd tg ts bg ltc4449 sw2 0.3h 0.22f tg2 bg2 3860 ta01 330f s 4 v out 1.2v 50a i avg
ltc3860 2 3860fc v cc voltage .................................................. C0.3v to 6v vinsns voltage ......................................... C0.3v to 30v vsnsn voltage ............................................ C0.3v to 2v run voltage ................................................ C0.3v to 6v isns1p , isns1n, isns2p , isns2n ........................... C0.3v to (v cc + 0.1v) all other voltages ......................... C0.3v to (v cc + 0.3v) operating junction temperature range (note 3) .................................................. C40c to 125c storage temperature range ................... C65c to 125c (note 1) 32 31 30 29 28 27 26 25 9 10 11 12 top view 33 sgnd uh package 32-lead (5mm s 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 v cc fb1 comp1 vsnsout vsnsn vsnsp comp2 fb2 run1 i lim1 isns1p isns1n isns2n isns2p i lim2 run2 track/ss1 vinsns sgnd sgnd i avg pgood1 pwmen1 pwm1 track/ss2 freq clkin clkout phsmd pgood2 pwmen2 pwm2 t jmax = 125c, ja = 34c/w exposed pad (pin 33) is sgnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range ltc3860euh#pbf ltc3860euh#trpbf 3860 32-lead (5mm 5mm) plastic qfn C40c to 125c ltc3860iuh#pbf ltc3860iuh#trpbf 3860 32-lead (5mm 5mm) plastic qfn C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ pin configuration absolute maximum ratings electrical characteristics the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c (note 3). v cc = 5v, v run1,2 = 5v, v freq = v clkin = 0v, v fb = 0.6v, f osc = 0.6mhz unless otherwise speci? ed. symbol parameter conditions min typ max units v cc input voltage range l 3.0 5.5 v v in v in range v cc = 5v l 324v i q input voltage supply current normal operation shutdown mode uvlo v run1,2 = 5v v run1,2 = 0v v cc < v uvlo 14 3.5 50 ma a ma v run run input threshold v run rising v run hysteresis 1.95 2.25 250 2.45 v mv i run run input pull-up current v run1,2 = 2.4v 1.5 a v uvlo undervoltage lockout threshold v cc rising v cc hysteresis l 100 3.0 v mv
ltc3860 3 3860fc electrical characteristics the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c (note 3). v cc = 5v, v run1,2 = 5v, v freq = v clkin = 0v, v fb = 0.6v, f osc = 0.6mhz unless otherwise speci? ed. symbol parameter conditions min typ max units i ss soft-start pin output current v ss = 0v 2.5 a t ss(internal) internal soft-start time 2ms v fb regulated feedback voltage 0c to 85c C40c to 85c C40c to 125c l 595.5 594 592.5 600 600 600 604.5 606 607.5 mv mv mv v fb /v cc regulated feedback voltage line dependence 3.0v < v cc < 5.5v 0.05 0.2 %/v i limit i lim pin output current v ilim = 0.8v 18 20 22 a power good v fb(ov) pgood/v fb overvoltage threshold v fb falling v fb rising 650 645 660 670 mv mv v fb(uv) pgood/v fb undervoltage threshold v fb falling v fb rising 530 540 555 550 mv mv v pgood(on) pgood pull-down resistance 15 60 error ampli? er i fb fb pin input current v fb = 600mv C100 100 na i out comp pin output current sourcing sinking 1 5 ma ma a v(ol) open-loop voltage gain 75 db sr slew rate 45 v/s f 0db comp unity-gain bandwidth 20 mhz differential ampli? er a v differential ampli? er voltage gain v vsnsn = 0v l 1.007 1 0.993 v/v v os input referred offset v vsnsn = 0v C2 2 mv sr slew rate 45 v/s f 0db bandwidth 20 mhz v out(max) maximum output voltage 4v current sense ampli? er v isense(max) maximum differential current sense voltage (v isnsp -v isnsn ) 50 mv a v(isense) voltage gain 18.5 v/v v cm(isense) input common mode range C0.3 v cc + 0.1 v i isense sense pin input current v cm = 1.5v 100 na v os current sense input referred offset 0c to 125c C40c to 125c l C2 C2.2 2 2.2 mv mv oscillator and phase-locked loop f osc oscillator frequency v clkin = 0v v freq = 0v v freq = 5v l l 360 540 400 600 440 660 khz khz v clkin = 5v r freq < 24.9k r freq = 30.1k r freq = 54.9k r freq = 75.0k 200 300 800 1.2 khz khz khz mhz maximum frequency minimum frequency 1.25 0.25 mhz mhz
ltc3860 4 3860fc electrical characteristics the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c (note 3). v cc = 5v, v run1,2 = 5v, v freq = v clkin = 0v, v fb = 0.6v, f osc = 0.6mhz unless otherwise speci? ed. symbol parameter conditions min typ max units i freq freq pin output current v freq = 0.8v 19 21 23 a t clkin(hi) clkin pulse width high v clkin = 0v to 5v 100 ns t clkin(lo) clkin pulse width low v clkin = 0v to 5v 100 ns r clkin clkin pull-up resistance 13 k v clkin clkin input threshold v clkin falling v clkin rising 1.2 2 v v v freq freq input threshold v clkin = 0v v freq falling v freq rising 1.5 2.5 v v v ol(clkout) clkout low output voltage i load = C500a 0.2 v v oh(clkout) clkout high output voltage i load = 500a v cc C 0.2 v 2 - 1 channel 1-to-channel 2 phase relationship v phsmd = 0v v phsmd = float v phsmd = v cc 180 180 120 deg deg deg clkout - 1 clkout-to-channel 1 phase relationship v phsmd = 0v v phsmd = float v phsmd = v cc 60 90 240 deg deg deg pwm/pwmen outputs pwm pwm output high voltage i load = 500a l 4.5 v pwm output low voltage i load = C500a l 0.5 v pwm output current in hi-z state 5 a pwm maximum duty cycle 91.5 % pwmen pwmen output high voltage i load = 1ma l 4.5 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? ja ) note 3: the ltc3860 is tested under pulsed load conditions such that t j t a . the ltc3860e is guaranteed to meet performance speci cations from 0? to 85? junction temperature. speci cations over the ?0? to 125? operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3860i is guaranteed over the full ?0? to 125? operating junction temperature range. the maximum ambient temperature consistent with these speci cations is determined by speci c operating conditions in conjunction with board layout, the rated package thermal resistors and other environmental factors.
ltc3860 5 3860fc load step transient response (single phase) load step transient response (2-phase) typical performance characteristics load step transient response (2-phase with 50% inductor mismatch) ef? ciency and power loss vs load current ef? ciency and power loss vs supply voltage 50s/div 3860 g01 v in = 12v v out = 1.2v i load step = 10a comp values: r2a = 6.8k, c1a = 470pf, c2a = 100pf v out 50mv/div i load 10a/div i l 10a/div load step transient response (2-phase) v out 50mv/div 50s/div 3860 g02 v in = 12v v out = 1.8v i load step = 10a i l1 5a/div i load 10a/div i l2 5a/div v out 50mv/div 50s/div 3860 g03 v in = 12v v out = 1.2v i load step = 10a i l1 5a/div i load 10a/div i l2 5a/div load current (a) 0.001 40 efficiency (%) power loss (w) 50 60 70 80 0.01 0.1 1 10 100 3860 g05 30 20 10 0 90 100 1 2 3 4 5 0 6 7 v in = 6v v out = 1.2v supply voltage (v) 6 70 efficiency (%) power loss (w) 72 76 78 80 90 84 8 10 11 3860 g06 74 86 88 82 1.0 1.5 2.5 3.0 3.5 6.0 4.5 2.0 5.0 5.5 4.0 79 12 13 14 v out = 1.2v i out = 15a v out(ac) 100mv/div 50s/div 3860 g04 v in = 12v v out = 1.2v i load = 0a to 25a i l1 = 320nh 10a/div i load 20a/div i l2 = 220nh 10a/div
ltc3860 6 3860fc typical performance characteristics oscillator frequency vs supply voltage supply voltage (v) 3.0 oscillator frequency (mhz) 1.175 1.200 1.225 4.5 5.5 3860 g11 1.150 1.125 1.100 3.5 4.0 5.0 1.250 1.275 1.300 short-circuit protection regulated v fb vs supply voltage oscillator frequency vs r freq 10ms/div 3860 g07 v in = 12v v out = 1.2v i load = shorted sw node 5v/div v out 1v/div supply voltage (v) 3 0.596 regulated v fb (v) 0.598 0.600 0.602 0.604 45 3860 g08 6 r freq (k) 0 oscillator frequency (mhz) 0.7 0.9 1.1 60 100 3860 g09 0.5 0.3 0.1 20 40 80 1.3 1.5 1.7 120 oscillator frequency vs temperature temperature (c) C50 oscillator frequency (khz) 595 600 605 25 50 75 100 125 3860 g10 590 585 C25 0 150 580 575 610
ltc3860 7 3860fc soft-start start-up ratiometric tracking start-up line step transient response (2-phase) 5ms/div 3860 g12 v in = 12v v out1 = 1.2v 0.1f capacitor on track/ss1 v out1 200mv/div coincident tracking start-up 2s/div 3860 g13 channel 1 tracking off pulse generator v out1 500mv/div track/ss1 500mv/div 2s/div 3860 g14 channel 1 tracking off pulse generator v out1 500mv/div track/ss1 500mv/div v out 50mv/div v in 5v/div comp1 100mv/div 20s/div 3860 g15 v in = 12v v out = 1.8v v in step = 7v to 14v i l1 5a/div i l2 5a/div line step transient response (2-phase) v out 50mv/div v in 5v/div comp1 100mv/div 20s/div 3860 g16 v in = 12v v out = 1.2v v in step = 7v to 14v i l1 5a/div i l2 5a/div line step transient response (single phase) 20s/div v out = 1.2v v in step = 7v to 14v 3860 g17 v out 50mv/div i l 2a/div v in 5v/div comp1 100mv/div typical performance characteristics
ltc3860 8 3860fc pin functions v cc (pin 1): chip supply voltage. bypass this pin to gnd with a capacitor (0.1f to 1f ceramic) in close proximity to the chip. fb1 (pin 2), fb2 (pin 8): error ampli? er inverting inputs. fb1 or fb2 can be connected to vsnsout via a resistor divider for remote v out sensing. the bottom of the divider should be connected to the sgnd pin of the ic. the other fb, when used, is typically connected to the other v out via a resistor divider, also terminated at the ic sgnd pin. comp1 (pin 3), comp2 (pin 7): error ampli? er outputs. pwm duty cycle increases with this control voltage. the error ampli? ers in the ltc3860 are true operational ampli? ers with low output impedance. as a result, the outputs of two active error ampli? ers cannot be directly connected together! for multiphase operation, connecting the fb pin on an error ampli? er to v cc will three-state the output of that ampli? er. multiphase operation can then be achieved by connecting all of the comp pins together and using one channel as the master and all others as slaves. vsnsout (pin 4): differential ampli? er output. vsnsn (pin 5): remote sense differential ampli? er inverting input. connect this pin to sense ground at the output load. vsnsp (pin 6): remote sense differential ampli? er noninverting input. connect this pin to v out at the output load. freq (pin 10): frequency set/select pin. if clkin is high, the resistor between this pin and sgnd sets the switching frequency. if clkin is low, the logic state of this pin sets frequency. this pin sources 21a. clkin (pin 11): external clock synchronization input pin. if an external clock is present at this pin, the switch- ing frequency will be synchronized to the external clock. otherwise, if high, a resistor from freq to sgnd sets frequency; if low, freq state sets frequency. clkout (pin 12): clock output pin. used to synchronize other ltc3860s. phsmd (pin 13): phase mode pin. selects ch1-ch2 and ch1-clkout phase relationship. isns1n (pin 21), isns2n (pin 20): current sense am- pli? er (C) input. the (C) input to the current ampli? er is normally connected to the respective v out . isns1p (pin 22), isns2p (pin 19): current sense ampli? er (+) input. the (+) input to the current sense ampli? er is normally connected to the midpoint of the inductors parallel rc sense circuit or to the node between the inductor and sense resistor if using a discrete sense resistor. i lim1 (pin 23), i lim2 (pin 18): current comparator sense voltage limit selection pin. connect a resistor from this pin to sgnd. this pin sources 20a. the resultant voltage sets the threshold for overcurrent protection. run1 (pin 24), run2 (pin 17): run control inputs. a voltage above 2.25v on either pin turns on the ic. how- ever, forcing either of these pins below 2v causes the ic to shut down that particular channel. there are 1.5a pull-up currents for these pins. pwm1 (pin 25), pwm2 (pin 16): (top) gate signal out- put. this signal goes to the pwm or top gate input of the external gate driver or integrated driver mosfet. this is a three-state compatible output. pwmen1/pwmen2 (pin 26/pin 15): enable pin for non- three-state compatible drivers. this pin has an internal open-drain pull-up to v cc . an external resistor to sgnd is required. this pin is low when the corresponding pwm pin is high impedance. pgood1 (pin 27), pgood2 (pin 14): power good pins. open-drain outputs that pull to ground when output volt- age is not in regulation. i avg (pin 28): average current output pin. a capacitor tied to ground from this pin stores a voltage proportional to the masters instantaneous average current when multiple outputs are paralleled. tie the i avg pin to ground when the controller drives two independent outputs. sgnd (pins 29, 30, exposed pad pin 33): ground. pins 29, 30 and 33 are electrically connected internally. the exposed pad must be soldered to the pcb for rated thermal performance. vinsns (pin 31): v in sense pin. connects to the v in power supply to provide line feedforward compensation.
ltc3860 9 3860fc functional diagram pin functions a change in v in immediately modulates the input to the pwm comparator and changes the pulse width in an in- versely proportional manner, thus bypassing the feedback loop and providing excellent transient line regulation. an external lowpass ? lter can be added to this pin to prevent noisy signals from affecting the loop gain. track/ss1 (pin 32), track/ss2 (pin 9): soft-start. the voltage ramp rate at these pins sets the voltage ramp rate of the outputs. self soft-start is accomplished by placing a capacitor to ground. 22 isns1p 21 isns1n 20 23 18 28 isns2n i avg i lim2 i lim1 20a 21a 20a 10 freq 13 phsmd 12 clkout 11 16 clkin 3860 bd oc1 noc1 oc2 noc2 19 isns2p x18.5 x18.5 8 fb2 7 comp2 9 track/ss2 ea2 ref ref 2 fb1 32 track/ss1 3 comp1 ea1 + + C + + C + C + C 5 vsnsn 24 run1 100k v cc 1.5a 1.5a v cc 17 run2 6 vsnsp 4 vsnsout da s v fb1 i lim1 v fb2 i lim2 s master/slave/ independent? sd/uvlo 27 pgood1 v fb1 v fb2 14 pgood2 ramp/slope/ feedforward pgood logic oc1 oc2 ov1 ov2 noc1 noc2 pwm2 31 vinsns 25 pwm1 15 pwmen2 26 pwmen1 pll/vco bg/bias v cc v cc v cc 100k v cc 1 v cc 29 sgnd 30 sgnd + +
ltc3860 10 3860fc operation (refer to functional diagram) main control architecture the ltc3860 is a dual-channel/dual-phase, constant frequency, voltage mode controller for dc/dc step-down applications. it is designed to be used in a synchronous switching architecture with external integrated-driver mosfets or external drivers and n-channel mosfets using single wire three-state pwm interfaces. the controller allows the use of sense resistors or lossless inductor dcr current sensing to maintain current balance between phases and to provide overcurrent protection. the operating frequency is selectable from 250khz to 1.25mhz. to multiply the effective switching frequency, multiphase operation can be extended to 3, 4, 6, or 12 phases by paralleling up to 6 controllers. in single or 3- phase operation, the 2nd or 4th channel can be used as an independent output. the output of the differential ampli? er is connected to the error ampli? er inverting input (fb) through a resistor divider. the remote sense differential ampli? er output (v snsout ) provides a signal equal to the differential voltage (v snsp C v snsn ) sensed across the output capacitor, but re-referenced to the local ground (sgnd). this permits accurate voltage sensing at the load, without regard to the potential difference between its ground and local ground. in the main voltage mode control loop, the error ampli- ? er output (comp) directly controls the converter duty cycle in order to drive the fb pin to 0.6v in steady state. dynamic changes in output load current can perturb the output voltage. when the output is below regulation, comp rises, increasing the duty cycle. if the output rises above regulation, comp will decrease, decreasing the duty cycle. as the output approaches regulation, comp will settle to the steady-state value representing the step- down conversion ratio. in normal operation, the pwm latch is set high at the begin- ning of the clock cycle (assuming comp > 0.5v). when the (line feedforward compensated) pwm ramp exceeds the comp voltage, the comparator trips and resets the pwm latch. if comp is less than 0.5v at the beginning of the clock cycle, as in the case of an overvoltage at the outputs, the pwm pin remains low throughout the entire cycle. when the pwm pin goes high it has a minimum on-time of approximately 20ns and a minimum off-time of approximately 1/12th the switching period. current sharing in multiphase operation, the ltc3860 also incorporates an auxiliary current sharing loop. inductor current is sampled each cycle. the masters current sense ampli? er output is averaged at the i avg pin. a small capacitor connected from i avg to gnd (typically 100pf) stores a voltage cor- responding to the instantaneous average current of the master. each phase integrates the difference between its current and the masters. within each phase the integrator output is proportionally summed with the system error ampli? er voltage (comp), adjusting that phases duty cycle to equalize the currents. when multiple ics are daisychained the i avg pins must be connected together . when the phases are operated independently, the i avg pin should be tied to ground. figure 1 shows a transient load step with 50% inductor mismatch in a 2-phase system. figure 1 v out(ac) 100mv/div 50s/div 3860 f01 v in = 12v v out = 1.2v i load = 0a to 25a i l1 = 320nh 10a/div i load 20a/div i l2 = 220nh 10a/div overcurrent protection the current sense ampli? er outputs also connect to overcurrent (oc) comparators that provide fault protec- tion in the case of an output short. when an oc fault is detected, the controller three-states the pwm output, resets the soft-start capacitor, and waits for 32768 clock cycles before attempting to start up again. the ltc3860 also provides negative oc (noc) protection by preventing turn-on of the bottom mosfet during a negative oc fault condition. the negative oc threshold is equal to C3/4 the positive oc threshold. see applications information for guidelines on setting these thresholds.
ltc3860 11 3860fc excellent transient response the ltc3860 error ampli? ers are true operational ampli- ? ers, meaning that they have high bandwidth, high dc gain, low offset and low output impedance. their bandwidth, when combined with high switching frequencies and low- value inductors, allows the compensation network to be optimized for very high control loop crossover frequencies and excellent transient response. the 600mv internal ref- erence allows regulated output voltages as low as 600mv without external level-shifting ampli? ers. line feedforward compensation the ltc3860 achieves outstanding line transient response using a feedforward correction scheme which instanta- neously adjusts the duty cycle to compensate for changes in input voltage, signi? cantly reducing output overshoot and undershoot. it has the added advantage of making the dc loop gain independent of input voltage. figure 2 shows how large transient steps at the input have little effect on the output voltage. shutdown control using the run pins the two channels of the ltc3860 can be independently enabled using the run1 and run2 pins. when both pins are driven low all internal circuitry, including the internal reference and oscillator, are completely shut down. a 1.5a pull-up current is provided for each run pin internally. the run pins remain low impedance up to v cc . from v cc to 6v, they may sink some current. undervoltage lockout to prevent operation of the power supply below safe input voltage levels, both channels are disabled when v cc is below the undervoltage lockout (uvlo) threshold (2.9v falling, 3v rising). if a run pin is driven high, the ltc3860 will start up the reference to detect when v cc rises above the uvlo threshold, and enable the appropriate channel. overvoltage protection if the output voltage rises to more than 10% above the set regulation value, which is re? ected as a v fb voltage of 0.66v or above, the ltc3860 will force the pwm output low to turn on the bottom mosfet and discharge the output. normal operation resumes once the output is back within the regulation window. however, if the reverse current ? owing from v out back through the bottom power mosfet to pgnd is greater than 3/4 the positive oc threshold, the noc comparator trips and shuts off the bottom power mosfet to protect it from being destroyed. this scenario can happen when the ltc3860 tries to start into a precharged load, higher than the ov threshold. as a result, the bottom switch turns on until the amount of reverse current trips the noc comparator threshold. internal soft-start by default, the start-up of each channels output voltage is normally controlled by an internal soft-start ramp. the internal soft-start ramp represents a noninverting input to the error ampli? er. the fb pin is regulated to the lower of the error ampli? ers three noninverting inputs (the internal soft-start ramp for that channel, the track/ss pin or the internal 600mv reference). as the ramp volt- age rises from 0v to 0.6v over approximately 2ms, the output voltage rises smoothly from its prebiased value to its ? nal set value. operation (refer to functional diagram) figure 2 20s/div v out = 1.2v v in step = 7v to 14v 3860 f02 v out 50mv/div i l 2a/div v in 5v/div comp1 100mv/div remote sense differential ampli? er the ltc3860 includes a low offset, unity gain, high bandwidth differential ampli? er for remote output sens- ing. output voltage accuracy is signi? cantly improved by removing board interconnection losses from the total error budget. the ltc3860 differential ampli? er has a typical output slew rate of 45v/s, bandwidth of 20mhz, input referred offset < 2mv and a typical maximum output voltage of v cc C 1v. the ampli? er is con? gured for unity gain, meaning that the differential voltage between v snsp and v snsn is translated to v snsout , relative to sgnd.
ltc3860 12 3860fc certain applications can result in the start-up of the converter into a non-zero load voltage, where residual charge is stored on the output capacitor at the onset of converter switching. in order to prevent the output from discharging under these conditions, the bottom mosfet is disabled until soft-start is complete. however, the bot- tom mosfet will be turned on for 20ns every 8 cycles to allow the driver ic to recharge its topside gate drive capacitor. soft-start and tracking using track/ss pin the user can connect an external capacitor greater than 10nf to the track/ss pin for the relevant channel to increase the soft-start ramp time beyond the internally set default. the track/ss pin represents a noninverting input to the error ampli? er and behaves identically to the internal ramp described in the previous section. an internal 2.5a current source charges the capacitor, creating a voltage ramp on the track/ss pin. as the track/ss pin voltage rises from 0v to 0.6v, the output voltage rises smoothly from 0v to its ? nal value in: c ss 0.6v 2.5? seconds alternatively, the track/ss pin can be used to force the start-up of v out to track the voltage of another supply. typically this requires connecting the track/ss pin to an external divider from the other supply to ground (see applications information). it is only possible to track another supply that is slower than the internal soft-start ramp. the track/ss pin also has an internal open-drain nmos pull-down transistor that turns on to reset the track/ss voltage when the channel is shut down (run = 0v or v cc < uvlo threshold) or during an oc fault condition. in multiphase operation, one master error ampli? er is used to control all of the pwm comparators. the fb pins for the unused error ampli? ers are connected to v cc in order to three-state these ampli? er outputs, and the comp pins are connected together. the track/ss pins should also be connected together so that the slave phases can detect when soft-start is complete and enable the bottom mosfet. frequency selection and the phase-locked loop (pll) the selection of the switching frequency is a trade-off between ef? ciency, transient response and component size. high frequency operation reduces the size of the inductor and output capacitor as well as increasing the maximum practical control loop bandwidth. however, ef? ciency is generally lower due to increased transition and switching losses. the ltc3860s switching frequency can be set in three ways: using an external resistor to linearly program the frequency, synchronizing to an external clock, or simply selecting one of two ? xed frequencies (400khz and 600khz). table 1 highlights these modes. table 1. frequency selection clkin pin freq pin frequency clocked r freq to gnd 250khz to 1.25mhz high r freq to gnd 250khz to 1.25mhz low low 400khz low high 600khz no external pll ? lter is required to synchronize the ltc3860 to an external clock. applying an external clock signal to the clkin pin will automatically enable the pll with internal ? lter. constant frequency operation brings with it a number of bene? ts: inductor and capacitor values can be chosen for a precise operating frequency and the feedback loop can be similarly tightly speci? ed. noise generated by the circuit will always be at known frequencies. using the clkout and phsmd pins in multiphase applications the ltc3860 features clkout and phsmd pins that al- low multiple ltc3860 ics to be daisychained together in multiphase applications. the clock output signal on the clkout pin can be used to synchronize additional ics in a 3-, 4-, 6- or 12-phase power supply solution feeding a single high current output, or even several outputs from the same input supply. the phsmd pin is used to adjust the phase relationship between channel 1 and channel 2, as well as the phase operation (refer to functional diagram)
ltc3860 13 3860fc relationship between channel 1 and clkout, as sum- marized in table 2. the phases are calculated relative to zero degrees, de? ned as the rising edge of pwm1. refer to applications information for more details on how to create multiphase applications. table 2. phase selection phsmd pin ch-1 to ch-2 phase ch-1 to clkout phase float 180 90 low 180 60 high 120 240 using the ltc3860 error ampli? ers in multiphase applications due to the low output impedance of the error ampli? ers, multiphase applications using the ltc3860 use one error ampli? er as the master with all of the slaves error ampli? ers disabled. the channel 1 error ampli? er (phase = 0) may be used as the master with phases 2 through n (up to 12) serving as slaves. to disable the slave error ampli? ers connect the fb pins of the slaves to v cc . this three-states the output stages of the ampli- ? ers. all comp pins should then be connected together to create pwm outputs for all phases. as noted in the section on soft-start, all track/ss pins should also be shorted together. refer to the multiphase operation sec- tion in applications information for schematics of various multiphase con? gurations. theory and bene? ts of multiphase operation multiphase operation provides several bene? ts over tra- ditional single phase power supplies: n greater output current capability n improved transient response n reduction in component size n increased real world operating ef? ciency because multiphase operation parallels power stages, the amount of output current available is n times what it would be with a single comparable output stage, where n is equal to the number of phases. the main advantages of polyphase operation are ripple current cancellation in the input and output capacitors, a faster load step response due to a smaller clock delay and reduced thermal stress on the inductors and mosfets due to current sharing between phases. these advantages allow for the use of a smaller size or a smaller number of components. power good indicator pins (pgood1, pgood2) each pgood pin is connected to the open drain of an internal pull-down device which pulls the pgood pin low when the corresponding fb pin voltage is outside the pgood regulation window (7.5% entering regula- tion, 10% leaving regulation). the pgood pins are also pulled low when the corresponding run pin is low, or during uvlo. in multiphase applications, one fb pin and error ampli? er are used to control all of the phases. pgood outputs for the slave phases may be left unconnected as they will not report fault conditions. pwm and pwmen pins the pwm pins are three-state compatible outputs, de- signed to drive mosfet drivers, drmoss, etc which do not represent a heavy capacitive load. an external resistor divider may be used to set the voltage to mid-rail while in the high impedance state. the pwmen outputs have an open-drain pull-up to v cc and require an appropriate external pull-down resistor. this pin is intended to drive the enable pins of the mosfet driv- ers that do not have three-state compatible pwm inputs. pwmen is low only when pwm is high impedance, and high at any other pwm state. operation (refer to functional diagram)
ltc3860 14 3860fc applications information setting the output voltage the ltc3860 regulates the fb pins to 0.6v. fb is con- nected to v out or v snsout (for remote output sensing) via an external resistive divider as shown in figure 3. the divider sets the output voltage according to the following equation: v out = 0.6v 1 + r b r a ? ? ? ? ? ? care should be taken to place the output divider resistors and the compensation components as close as possible to the fb pin to minimize switching noise coupling into the control signal path. programming the operating frequency the ltc3860 can be hard wired to one of two ? xed fre- quencies, linearly programmed to any frequency between 250khz and 1.25mhz or synchronized to an external clock. table 1 in the operation section shows how to connect the clkin and freq pins to choose the mode of frequency programming. in linear programming mode the frequency of operation is given by the following equation: frequency (r freq C 15k) ? 20hz/ ^ figure 4 shows operating frequency vs r freq . comp ltc3860 fb r a r b v out divider and compensation components placed near fb, sgnd and comp pins c out 3860 f03 sgnd figure 3. output divider and compensation component placement sensing the output voltage with a differential ampli? er when using the remote sense differential ampli? er, care should be taken to route the v snsp and v snsn pcb traces parallel to each other all the way to the terminals of the output capacitor or remote sensing points on the board. in addition, avoid routing these sensitive traces near any high speed switching nodes in the circuit. ideally, they should be shielded by a low impedance ground plane to maintain signal integrity. when using a single ltc3860 to regulate two output voltages, the negative terminal of v out2 should be kelvin-connected to sgnd and the differential ampli? er should be used to remotely sense v out1 . this will maxi- mize output voltage accuracy for both channels. figure 4. operating frequency vs r freq frequency synchronization the ltc3860 incorporates an internal phase-locked loop (pll) which enables synchronization of the internal os- cillator (rising edge of pwm1) to an external clock from 250khz to 1.25mhz. since the entire pll is internal to the ltc3860, simply applying a cmos level clock signal to the clkin pin will enable frequency synchronization. a resistor from freq to gnd is still required to set the free running frequency close to the sync input frequency. r freq (k) 0 oscillator frequency (mhz) 0.7 0.9 1.1 60 100 3860 f04 0.5 0.3 0.1 20 40 80 1.3 1.5 1.7 120
ltc3860 15 3860fc applications information choosing the inductor and setting the current limit the inductor value is related to the switching frequency, which is chosen based on the trade-offs discussed in the operation section. the inductor can be sized using the following equation: l = v out f i l ? ? ? ? ? ? ? ? v out v in ? ? ? ? ? ? choosing a larger value of i l leads to smaller l, but re- sults in greater core loss (and higher output voltage ripple for a given output capacitance and/or esr). a reasonable starting point for setting the ripple current is 30% of the maximum output current, or: i l = 0.3 ? i out the inductor saturation current rating needs to be higher than the peak inductor current during transient conditions. if i out is the maximum rated load current, then the maxi- mum transient current, i max , would normally be chosen to be some factor (e.g., 60%) greater than i out : i max = 1.6 ? i out the minimum saturation current rating should be set to allow margin due to manufacturing and temperature varia- tion in the sense resistor or inductor dcr. a reasonable value would be: i sat = 2.2 ? i out the programmed current limit must be low enough to ensure that the inductor never saturates and high enough to allow increased current during transient conditions and allow margin for dcr variation. for example, if: i sat = 2.2 ? i out and i max = 1.6 ? i out a reasonable i limit would be: i limit = 2 ? i out if the sensed inductor current exceeds current limit, the ic will three-state the pwm outputs, reset the soft-start timer and wait 32768 switching cycles before attempting to return the output to regulation. the current limit is programmed using a resistor from the i lim pin to sgnd. the i lim pin sources 20a to generate a voltage corresponding to the current limit. the current sense circuit has a voltage gain of 20 and a zero current level of 500mv. therefore, the current limit resistor should be set using the following equation: r ilim = 18.5 i limit(set) ? sense + 0.53v 20? in multiphase applications only one current limit resistor should be used per ltc3860. the i lim2 pin should be tied to v cc . internal logic will then cause channel 2 to use the same current limit levels as channel 1. if an ltc3860 has a slave and an independent, then both i lim pins must be independently set to the right voltage. inductor core selection once the value of l is known, the type of inductor must be selected. high ef? ciency converters generally cannot afford the core losses found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. also, core losses decrease as inductance increases. unfortunately, increased inductance requires more turns of wire, larger inductance and larger copper losses. ferrite designs have very low core loss and are preferred at high switching frequencies. however, these core materials exhibit hard saturation, causing an abrupt reduction in the inductance when the peak current capability is exceeded. do not allow the core to saturate! c in selection the input bypass capacitor in an ltc3860 circuit is com- mon to both channels. the input bypass capacitor needs to meet these conditions: its esr must be low enough to keep the supply drop low as the top mosfets turn on, its rms current capability must be adequate to withstand the ripple current at the input, and the capacitance must be large enough to maintain the input voltage until the input
ltc3860 16 3860fc applications information supply can make up the difference. generally, a capacitor (particularly a non-ceramic type) that meets the ? rst two parameters will have far more capacitance than is required to keep capacitance-based droop under control. the input capacitors voltage rating should be at least 1.4 times the maximum input voltage. power loss due to esr occurs not only as i 2 r dissipation in the capacitor itself, but also in overall battery ef? ciency. for mobile applica- tions, the input capacitors should store adequate charge to keep the peak battery current within the manufacturers speci? cations. the input capacitor rms current requirement is simpli- ? ed by the multiphase architecture and its impact on the worst-case rms current drawn through the input network (battery/fuse/capacitor). it can be shown that the worst- case rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used to determine the maximum rms current requirement. increasing the output current drawn from the other out-of-phase controller will actually decrease the input rms ripple current from this maximum value. the out-of-phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in continuous mode, the source current of the top n-channel mosfet is approximately a square wave of duty cycle v out /v in . the maximum rms capacitor current is given by: i rms i out(max) v out v in ? out () v in this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even signi? cant deviations do not offer much relief. the total rms current is lower when both controllers are operating due to the interleav- ing of current pulses through the input capacitors. this is why the input capacitance requirement calculated above for the worst-case controller is adequate for the dual controller design. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. ceramic, tantalum, os-con and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramics have high voltage coef? cients of capacitance and may have audible piezoelectric effects; tantalums need to be surge-rated; os-cons suffer from higher inductance, larger case size and limited surface mount applicability; and electrolytics higher esr and dryout possibility require several to be used. sanyo os-con svp , svpd series; sanyo poscap tqc series or aluminum electrolytic capacitors from panasonic wa series or cornell dubilier spv series, in parallel with a couple of high performance ceramic capacitors, can be used as an effective means of achieving low esr and high bulk capacitance. c out selection the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the output ripple v out is approximately bounded by: v out ? i l esr + 1 8f sw ? out ? ? ? ? ? ? where i l is the inductor ripple current. i l may be calculated using the equation: i l = v out l? sw 1 v out v in ? ? ? ? ? ? since il increases with input voltage, the output ripple voltage is highest at maximum input voltage. typically, once the esr requirement is satis? ed, the capacitance is adequate for ? ltering and has the necessary rms current rating.
ltc3860 17 3860fc applications information manufacturers such as sanyo, panasonic and cornell du- bilier should be considered for high performance through- hole capacitors. the os-con semiconductor electrolyte capacitor available from sanyo has a good (esr)(size) product. an additional ceramic capacitor in parallel with os-con capacitors is recommended to offset the effect of lead inductance. in surface mount applications, multiple capacitors may have to be paralleled to meet the esr or transient current handling requirements of the application. aluminum elec- trolytic and dry tantalum capacitors are both available in surface mount con? gurations. new special polymer surface mount capacitors offer very low esr also but have much lower capacitive density per unit volume. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. several excellent output capacitor choices include the sanyo poscap tpd, tpe, tpf series, the kemet t520, t530 and a700 series, nec/tokin neocapacitors and panasonic sp series. other capacitor types include nichicon pl series and sprague 595d series. consult the manufacturer for other speci? c recommendations. current sensing to maximize ef? ciency the ltc3860 is designed to sense current through the inductors dcr, as shown in figure 6. the dcr of the inductor represents the small amount of dc winding resistance of the copper, which for most inductors applicable to this application, is between 0.3 and 1m. if the ? lter rc time constant is chosen to be exactly equal to the l/dcr time constant of the inductor, the voltage drop across the external capacitor is equal to the voltage drop across the inductor dcr. check the manufacturers data sheet for speci? cations regarding the inductor dcr in order to properly dimension the external ? lter components. the dcr of the inductor can also be measured using a good rlc meter. since the temperature coef? cient of the inductors dcr is 3900ppm/c, ? rst order compensation of the ? lter time constant is possible by using ? lter resistors with an equal but opposite (negative) tc, assuming a low tc capacitor is used. that is, as the inductors dcr rises with increasing temperature, the l/dcr time constant drops. since we want the ? lter rc time constant to match the l/dcr time constant, we also want the ? lter rc time constant to drop with increasing temperature. typically, the inductance will also have a small negative tc. the isnsp and isnsn pins are the inputs to the current comparators. the common mode range of the current comparators is C0.3v to v cc + 0.1v. continuous linear operation is provided throughout this range, allowing output voltages between 0.6v (the reference input to the error ampli? ers) and v cc + 0.1v. the maximum differential current sense input (v isnsp C v isnsn ) is 50mv. the high impedance inputs to the current comparators allow accurate dcr sensing. however, care must be taken not to ? oat these pins during normal operation. filter components mutual to the sense lines should be placed close to the ltc3860, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure 5). sensing current elsewhere can effectively add parasitic induc- tance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if low value (<5m) sense resistors are used, verify that the signal across c f resembles the current through the inductor, and reduce r f to eliminate any large step as- sociated with the turn-on of the primary switch. if dcr sensing is used (figure 6b), sense resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. the capacitor c1 should be placed close to the ic pins. c out to sense filter, next to the controller inductor or r sense 3860 f05 figure 5. sense lines placement with inductor or sense resistor
ltc3860 18 3860fc applications information multiphase operation when the ltc3860 is used in a single output, multiphase application, the slave error ampli? ers must be disabled by connecting their fb pins to v cc . all current limits should be set to the same value using only one resistor to sgnd per ic. i lim2 should then be connected to v cc . these connections are shown in table 3. in a multiphase application all comp , run and track/ss pins must be connected together. for output loads that demand high current, multiple ltc3860s can be daisychained to run out of phase to provide more output current without increasing input and output voltage ripple. the clkin pin allows the ltc3860 to synchronize to the clkout signal of another ltc3860. the clkout signal can be connected to the clkin pin of the following ltc3860 stage to line up both the frequency and the phase of the entire system. tying the phsmd pin to v cc , sgnd or ? oating it generates a phase difference (between clkin and clkout) of 240, 60 or 90 respec- tively, and a phase difference (between ch1 and ch2) of 120, 180 or 180. figure 7 shows the phsmd connections necessary for 3-, 4-, 6- or 12-phase operation. a total of 12 phases can be daisychained to run simultaneously out of phase with respect to each other. boost tg ltc4449 v in 12v ts v out 3860 f06a r s esl l sense resistor plus parasitic inductance filter components placed near sense pins c f ? 2r f esl/r s pole-zero cancellation v logic v cc 5v in bg gnd r f c f r f vinsns v cc pwm isnsp isnsn ltc3860 gnd (6a) using a resistor to sense current boost tg ltc4449 v in 12v ts v out 3860 f06b dcr l r1* inductor v logic v cc 5v in *place r1 near inductor place c1 near isnsp , isnsn pins bg gnd c1* vinsns v cc pwm isnsp isnsn ltc3860 gnd r1 ? c1 = l dcr (6b) using the inductor to sense current figure 6. two different methods of sensing current table 3. multiphase con? gurations ch1 ch2 fb1 fb2 i lim1 i lim2 master slave on off (fb = v cc ) resistor to gnd v cc slave slave off (fb = v cc ) off (fb = v cc ) resistor to gnd v cc slave additional output off (fb = v cc ) on resistor to gnd resistor to gnd
ltc3860 19 3860fc applications information figure 7a. 3-phase operation figure 7b. 4-phase operation figure 7c. 6-phase operation figure 7d. 12-phase operation clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3860 v cc v cc 0, 120 +240 v snsout1 v snsout2 clkout comp1 comp2 track/ss1,2 clkin phsmd fb1 fb2 i lim2 i lim1 i avg 3960 f07a ltc3860 240, 60 clkout track/ss2 comp1 comp2 track/ss1 clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3860 v cc v cc 0, 180 +90 v snsout1 clkout comp1 comp2 track/ss1,2 clkin phsmd fb1 fb2 i lim2 i lim1 i avg 3960 f07b ltc3860 90, 270 clkout comp1 comp2 track/ss1,2 clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3860 v cc v cc 0, 180 +60 +60 v snsout1 clkout comp1 comp2 track/ss1,2 clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3860 60, 240 clkout comp1 comp2 track/ss1,2 v cc clkin phsmd fb1 fb2 i lim2 i lim1 i avg 3960 f07c ltc3860 120, 300 clkout comp1 comp2 track/ss1,2 clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3860 v cc v cc 0, 180 +60 v snsout1 clkout comp1 comp2 track/ss1,2 clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3860 60, 240 clkout comp1 comp2 track/ss1,2 v cc +60 +90 clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3860 120, 300 clkout comp1 comp2 track/ss1,2 clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3860 v cc v cc 210, 30 +60 clkout comp1 comp2 track/ss1,2 clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3860 270, 90 clkout comp1 comp2 track/ss1,2 v cc +60 clkin phsmd fb1 fb2 i lim2 i lim1 i avg 3960 f07d ltc3860 330, 150 clkout comp1 comp2 track/ss1,2
ltc3860 20 3860fc applications information a multiphase power supply signi? cantly reduces the amount of ripple current in both the input and output ca- pacitors. the rms input ripple current is divided by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output volt- age). the output ripple amplitude is also reduced by the number of phases used. figure 8 graphically illustrates the principle. 3860 f08 sw1 v i cin i cout single phase sw1 v sw2 v i cin i l2 i l1 i cout dual phase ripple figure 8. single and 2-phase current waveforms duty factor (v out /v in ) 0.1 di c(p-p) v o /l 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.3 0.5 0.6 3860 f09 0.2 0.4 0.7 0.8 0. 9 1 phase 2 phase figure 9. normalized output ripple current vs duty factor [i rms ? 0.3 (di c(pp) )] 0 0.1 0.2 0.3 0.4 3860 f10 0.5 0.6 duty factor (v out /v in ) 0.1 rms input ripple current dc load current 0.3 0.5 0.6 0.2 0.4 0.7 0.8 0.9 1 phase 2 phase figure 10. normalized rms input ripple current vs duty factor for 1 and 2 output stages the worst-case rms ripple current for a single stage de- sign peaks at an input voltage of twice the output voltage. the worst case rms ripple current for a two stage design results in peak outputs of 1/4 and 3/4 of input voltage. when the rms current is calculated, higher effective duty factor results and the peak current levels are divided as long as the current in each stage is balanced. refer to application note 19 for a detailed description of how to calculate rms current for the single stage switching regulator. figures 9 and 10 illustrate how the input and output currents are reduced by using an additional phase. for a 2-phase converter, the input current peaks drop in half and the frequency is doubled. the input capacitor requirement is thus reduced theoretically by a factor of four! just imagine the possibility of capacitor savings with even higher number of phases! output current sharing when multiple ltc3860s are daisychained to drive a com- mon load, accurate output current sharing is essential to achieve optimal performance and ef? ciency. otherwise, if one stage is delivering more current than another, then the temperature between the two stages will be different, and that could translate into higher switch r ds(on) , lower ef? ciency, and higher rms ripple. when the comp and i avg pins of multiple ltc3860s are tied together, the amount of output current delivered from each ltc3860 is actively balanced by the i ave loop. the sgnd pins of the multiple ltc3860s must be kelvined to the same point for optimal current sharing.
ltc3860 21 3860fc dual-channel operation the ltc3860 can control two independent power supply outputs with no channel-to-channel interaction or jitter. the following recommendations will ensure maximum performance in this mode of operation: n the output of channel 1 should be sensed using the remote sense differential ampli? er. the sgnd pins and exposed pad and all local small-signal gnd should then be a kelvin connection to the negative terminal of the channel 2 output. this will provide the best possible regulation on channel 2 without adversely affecting channel 1. n due to internal logic used to determine the mode of operation, separate current limit resistors should be used for each channel in dual-channel operation, even when the values are the same. table 4 shows the i lim and ea con? guration for dual- channel operation. table 4. dual-channel con? guration ch1 ch2 ea1 ea2 i lim1 i lim2 independent independent on on resistor to gnd resistor to gnd tracking and soft-start (track/ss pins) the start-up of the supply output is controlled by the volt- age on the track/ss pin for that channel. the ltc3860 regulates the fb pin voltage to the lower of the voltage on the track/ss pin and the internal 600mv reference. applications information the track/ss pin can therefore be used to program an external soft-start function or allow the output supply to track another supply during start-up. external soft-start is enabled by connecting a capacitor from the track/ss pin to sgnd. an internal 2.5a current source charges the capacitor, creating a linear voltage ramp at the track/ss pin, and causing the output supply to rise smoothly from its prebiased value to its ? nal regulated value. the total soft-start time is approximately: t ss = c ss 600mv 2.5? alternatively, the track/ss pin can be used to track another supply during start-up. for example, figure 11a shows the start-up of v out2 con- trolled by the voltage on the track/ss2 pin. normally this pin is used to allow the start-up of v out2 to track that of v out1 as shown qualitatively in figures 11a and 11b. when the voltage on the track/ss2 pin is less than the internal 0.6v reference, the ltc3860 regulates the fb2 voltage to ltc3860 fb2 v out2 v out1 fb1 track/ss2 r2b r2a 3860 f11a r1b r1a r tracka r trackb figure 11b and 11c. two different modes of output voltage tracking figure 11a. using the track/ss pin time ( 11b ) coincident trackin g v out1 v out2 output voltage time 3860 f11b_c ( 11c ) ratiometric trackin g v out1 v out2 output voltage
ltc3860 22 3860fc the track/ss2 pin voltage instead of 0.6v. the start-up of v out2 may ratiometrically track that of v out1 , according to a ratio set by a resistor divider (figure 11c): v out1 v out2 = r2a r tracka r tracka + r trackb r2b + r2a for coincident tracking (v out1 = v out2 during start-up), r2a = r tracka r2b = r trackb the ramp time for v out2 to rise from 0v to its ? nal value is: t ss2 = t ss1 0.6 v out1f r tracka + r trackb r tracka for coincident tracking, t ss2 = t ss1 v out2f v out1f where v out1f and v out2f are the ? nal, regulated values of v out1 and v out2 . v out1 should always be greater than v out2 when using the track/ss2 pin for tracking. if no tracking function is desired, then the track/ss2 pin may be tied to a capacitor to ground, which sets the ramp time to ? nal regulated output voltage. it is only possible to track another supply that is slower than the internal soft-start ramp. at the completion of tracking, the track/ss pin must be >620mv, so as not to affect regulation accuracy and to ensure the part is in ccm mode. applications information feedback loop compensation the ltc3860 is a voltage mode controller with a second dedicated current sharing loop to provide excellent phase- to-phase current sharing in multiphase applications. the current sharing loop is internally compensated. while type 2 compensation for the voltage control loop may be adequate in some applications (such as with the use of high esr bulk capacitors), type 3 compensation, along with ceramic capacitors, is recommended for opti- mum transient response. referring to figure 12, the error ampli? ers sense the output voltage at v out . the positive input of the error ampli? er is connected to an internal 600mv reference, while the negative input is connected to the fb pin. the output is connected to comp , which is in turn connected to the line feedforward circuit and from there to the pwm generator. to speed up the overshoot recovery time, the maximum potential at the comp pin is internally clamped. unlike many regulators that use a transconductance (g m ) ampli? er, the ltc3860 is designed to use an inverting summing ampli? er topology with the fb pin con? gured as a virtual ground. this allows the feedback gain to be tightly controlled by external components, which is not possible with a simple g m ampli? er. in addition, the voltage feedback ampli? er allows ? exibility in choosing pole and zero locations. in particular, it allows the use of type 3 compensation, which provides a phase boost at the lc pole frequency and signi? cantly improves the control loop phase margin. C + v out v ref r1 r3 c3 r2 c1 gain (db) c2 fb r b comp freq C1 C1 +1 gain phase boost 0 phase (deg) C90 C180 C270 C380 3806 f12 figure 12. type 3 ampli? er compensation
ltc3860 23 3860fc applications information in a typical ltc3860 circuit, the feedback loop consists of the line feedforward circuit, the modulator, the external inductor, the output capacitor and the feedback ampli? er with its compensation network. all these components affect loop behavior and need to be accounted for in the loop compensation. the modulator consists of the pwm generator, the output mosfet drivers and the external mosfets themselves. the modulator gain varies linearily with the input voltage. the line feedforward circuit com- pensates for this change in gain, and provides a constant gain from the error ampli? er output to the inductor input regardless of input voltage. from a feedback loop point of view, the combination of the line feedforward circuit and the modulator looks like a linear voltage transfer function from comp to the inductor input. it has fairly benign ac behavior at typical loop compensation frequencies with signi? cant phase shift appearing at half the switching frequency. the external inductor/output capacitor combination makes a more signi? cant contribution to loop behavior. these components cause a second order lc roll-off at the output with 180 phase shift. this roll-off is what ? lters the pwm waveform, resulting in the desired dc output voltage, but this phase shift causes stability issues in the feedback loop and must be frequency compensated. at higher frequen- cies, the reactance of the output capacitor will approach its esr, and the roll-off due to the capacitor will stop, leaving C20db/decade and 90 of phase shift. figure 12 shows a type 3 ampli? er. the transfer function of this ampli? er is given by the following equation: v comp v out = ? + sc1r2 () 1 + s(r1 + r3)c3 [] sr1 c1 + c2 () 1 + s(c1//c2)r2 ? ? ? ? 1 + sc3r3 () the rc network across the error ampli? er and the feed- forward components r3 and c3 introduce two pole-zero pairs to obtain a phase boost at the system unity-gain frequency, f c . in theory, the zeros and poles are placed symmetrically around f c , and the spread between the zeros and the poles is adjusted to give the desired phase boost at f c . however, in practice, if the crossover frequency is much higher than the lc double-pole frequency, this method of frequency compensation normally generates a phase dip within the unity bandwidth and creates some concern regarding conditional stability. if conditional stability is a concern, move the error ampli- ? ers zero to a lower frequency to avoid excessive phase dip. the following equations can be used to compute the feedback compensation components value: f sw = switching frequency f lc = 1 2 lc out f esr = 1 2 r esr c out choose: f c = crossover frequency = f sw 10 f z1(err) = f lc = 1 2 r2c1 f z2(res) = f c 5 = 1 2 r1 + r3 () c3 f p1(err) = f esr = 1 2 r2(c1// c2) f p2(res) = 5f c = 1 2 r3c3 required error ampli? er gain at frequency f c : a 40log 1 + f c f lc ? ? ? ? ? ? 2 20log 1 + f c f esr ? ? ? ? ? ? 2 20log a mod () 20log r2 r1 1 + f lc f c ? ? ? ? ? ? 1 + f p2(res) f c + f p2(res) ? z2(res) f z2(res) ? ? ? ? ? ? 1 + f c f esr + f lc f esr ? lc ? ? ? ? ? ? 1 + f p2(res) f c ? ? ? ? ? ? where amod is the modulator and line feedforward gain and is equal to: a mod v in(max) ?c max v saw 12v/v
ltc3860 24 3860fc applications information once the value of resistor r1, poles and zeros location have been decided, the value of r2, c1, c2, r3 and c3 can be obtained from the previous equations. compensating a switching power supply feedback loop is a complex task. the applications shown in this data sheet show typical values, optimized for the power components shown. though similar power compon- ents should suf? ce, substantially changing even one major power component may degrade performance signi? cantly. stability also may depend on circuit board layout. to verify the calculated component values, all new circuit designs should be prototyped and tested for stability. inductor the inductor in a typical ltc3860 circuit is chosen for a speci? c ripple current and saturation current. given an input voltage range and an output voltage, the inductor value and operating frequency directly determine the ripple current. the inductor ripple current in the buck mode is: i l = v out (f)(l) 1 v out v in ? ? ? ? ? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. thus highest ef? ciency operation is obtained at low frequency with small ripple current. to achieve this however, requires a large inductor. a reasonable starting point is to choose a ripple cur- rent between 20% and 40% of i o(max) . note that the largest ripple current occurs at the highest v in . to guar- antee that ripple current does not exceed a speci? ed maximum, the inductor in buck mode should be chosen according to: l v out f i l(max) 1 v out v in(max) ? ? ? ? ? ? power mosfet selection the ltc3680 requires at least two external n-channel power mosfets per channel, one for the top (main) switch and one or more for the bottom (synchronous) switch. the number, type and on-resistance of all mosfets selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the mosfet will be used. a much smaller and much lower input capacitance mosfet should be used for the top mosfet in applications that have an output voltage that is less than 1/3 of the input voltage. in applications where v in >> v out , the top mosfets on-resistance is normally less important for overall ef? ciency than its input capaci- tance at operating frequencies above 300khz. mosfet manufacturers have designed special purpose devices that provide reasonably low on-resistance with signi? cantly reduced input capacitance for the main switch application in switching regulators. selection criteria for the power mosfets include the on- resistance r ds(on) , input capacitance, breakdown voltage and maximum output current. for maximum ef? ciency, on-resistance r ds(on) and input capacitance should be minimized. low r ds(on) minimizes conduction losses and low input capacitance minimizes switching and transition losses. mosfet input capacitance is a combination of several components but can be taken from the typical gate charge curve included on most data sheets (figure 13). + C v ds v in v gs miller effect q in ab c miller = (q b C q a )/v ds v gs v + C 3860 f12 figure 13. gate charge characteristic
ltc3860 25 3860fc applications information the curve is generated by forcing a constant input cur- rent into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. the initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. the ? at portion of the curve is the result of the miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. the upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is ? at) is speci? ed for a given v ds drain voltage, but can be adjusted for different v ds voltages by multiplying by the ratio of the application v ds to the curve speci? ed v ds values. a way to estimate the c miller term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated v ds voltage speci? ed. c miller is the most important selection criteria for determining the transition loss term in the top mosfet but is not directly speci? ed on mosfet data sheets. c rss and c os are speci? ed sometimes but de? nitions of these parameters are not included. when the controller is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out v in synchronous switch duty cycle = v in ? out v in the power dissipation for the main and synchronous mosfets at maximum output current are given by: p main = v out v in i max () 2 (1 + )r ds(on) + v in 2 i max 2 (r dr )(c miller ) 1 v cc ? th(il) + 1 v th(il) ? ? ? ? ? ? ? ? (f) p sync = v in ? v out v in (i max ) 2 (1 + )r ds(0n) where is the temperature dependency of r ds(on) , r dr is the effective top driver resistance, v in is the drain po- tential and the change in drain potential in the particular application. v th(il) is the data sheet speci? ed typical gate threshold voltage speci? ed in the power mosfet data sheet at the speci? ed drain current. c miller is the calculated capacitance using the gate charge curve from the mosfet data sheet and the technique previously described. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve. typical values for range from 0.005/c to 0.01/c depending on the particular mosfet used. multiple mosfets can be used in parallel to lower r ds(on) and meet the current and thermal requirements if desired. suitable drivers such as the ltc4449 are capable of driv- ing large gate capacitances without signi? cantly slowing transition times. in fact, when driving mosfets with very low gate charge, it is sometimes helpful to slow down the drivers by adding small gate resistors (5 or less) to reduce noise and emi caused by the fast transitions mosfet driver selection gate driver ics, drmoss and power blocks with an interface compatible with the ltc3860s three-state pwm outputs or the ltc3860s pwm/pwmen outputs can be used.
ltc3860 26 3860fc applications information ef? ciency considerations the ef? ciency of a switching regulator is equal to the output power divided by the input power. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. percent ef? ciency can be expressed as: %ef? ciency = 100% - (l1 + l2 + l3 + ) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the system produce losses, three main sources usually account for most of the losses in ltc3860 applications: 1) i 2 r losses, 2) topside mosfet transition losses, 3) gate drive current. 1. i 2 r losses occur mainly in the dc resistances of the mosfet, inductor, pcb routing, and input and output capacitor esr. since each mosfet is only on for part of the cycle, its on-resistance is effectively multiplied by the percentage of the cycle it is on. therefore in high step-down ratio applications the bottom mosfet should have a much lower r ds(on) than the top mosfet. it is crucial that careful attention is paid to the layout of the power path on the pcb to minimize its resistance. in a 2-phase, 1.2v output, 60a system, 1m of pcb resistance at the output costs 5% in ef? ciency. 2. transition losses apply only to the topside mosfet but in 12v input applications are a very signi? cant source of loss. they can be minimized by choosing a driver with very low drive resistance and choosing a mosfet with low q g , r g and c rss . 3. gate drive current is equal to the sum of the top and bottom mosfet gate charges multiplied by the fre- quency of operation. however, many drivers employ a linear regulator to reduce the input voltage to a lower gate drive voltage. this multiplies the gate loss by that step down ratio. in high frequency applications it may be worth using a secondary user supplied rail for gate drive to avoid the linear regulator. other sources of loss include body or schottky diode conduction during the driver dependent non-overlap time and inductor core losses. design example as a design example, consider a 2-phase application where v in = 12v, v out = 1.2v, i load = 50a and f switch = 600khz. assume that a secondary 5v supply is available for the ltc3860 v cc supply. the inductance value is chosen based on a 30% ripple assumption. each channel supplies an average 25a to the load resulting in 7.5a peak-peak ripple: i l = v out ? v out v in ? ? ? ? ? ? fl a 240nh inductor per phase will create 7.5a peak-to-peak ripple. a 0.3h inductor with a dcr of 0.7m typical is selected from the vishay ihlp5050fd-01 series. connect clkin to sgnd and freq to v cc to select 600khz operation. setting i limit = 50a per phase leaves plenty of headroom for transient conditions while still adequately protecting against inductor saturation. this corresponds to: r ilim = 18.5 50a 0.7m + 0.53v 20? = 58.8k choose 59.0k. for the dcr sense ? lter network, we can choose r = 2.0k and c = 220nf to match the l/dcr time constant of the inductor. a loop crossover frequency of 100khz provides good transient performance while still being well below the switching frequency of the converter. four 330f 9m poscaps are chosen for the output capacitors to maintain supply regulation during severe transient conditions and to minimize output voltage ripple. the following compensation values (figure 12) were determined empirically: r1 = 10k r2 = 6.04k r3 = 698 c1 = 680pf c2 = 47pf c3 = 390pf
ltc3860 27 3860fc applications information to set the output voltage equal to 1.2v: r b = 10k the renesas r2j20602np integrated-driver mosfet is chosen for the power stages because of its high ef? ciency and high level of integration. printed circuit board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the converter. 1. the connection between the sgnd pin on the ltc3860 and all of the small-signal components surrounding the ic should be isolated from the system power ground. place all decoupling capacitors, such as the ones on v cc , between isnsp and isnsn etc., close to the ic. in multiphase operation sgnd should be kelvin-connected to the main ground node near the bottom terminal of the input capacitor. in dual-channel operation, sgnd should be kelvin-connected to the bottom terminal of the output capacitor for channel 2, and channel 1 should be remotely sensed using the remote sense differential ampli? er. 2. place the small-signal components away from high frequency switching nodes on the board. the ltc3860 contains remote sensing of output voltage and inductor current and logic-level pwm outputs enabling the ic to be isolated from the power stage. 3. the pcb traces for remote voltage and current sense should avoid any high frequency switching nodes in the circuit and should ideally be shielded by ground planes. each pair (v snsp and v snsn , i snsp and i snsn ) should be routed parallel to one another with minimum spacing between them. if dcr sensing is used, place the top resistor (figure 6b, r1) close to the switching node. 4. the input capacitor should be kept as close as possible to the power mosfets. the loop from the input capaci- tors positive terminal, through the mosfets and back to the input capacitors negative terminal should also be as small as possible. 5. if using discrete drivers and mosfets, check the stress on the mosfets by independently measuring the drain-to-source voltages directly across the device terminals. beware of inductive ringing that could exceed the maximum voltage rating of the mosfet. if this ringing cannot be avoided and exceeds the maximum rating of the device, choose a higher voltage rated mosfet. 6. when cascading multiple ltc3860 ics, minimize the capacitive load on the clkout pin to minimize phase error. kelvin all the ltc3860 ic grounds to the same point, typically sgnd of the ic containing the master.
ltc3860 28 3860fc typical applications dual output with drmos fb1 comp1 vsnsout vsnsn vsnsp comp2 fb2 v diff1 v os1n v os1p i lim1 isns1p isns1n isns2n isns2p i lim2 run2 track/ss2 freq clkin clkout phsmd pgood2 pwm2 v cc track/ss1 vinsns i avg pgood1 pwm1 run1 ltc3860 sgnd pwmen1,2 470pf 220 v diff1 v out2 v cc v cc v cc v cin disable pwm v in r2j20602 reg5v boot sw1 sw2 v swh v ldrv 2.2 2.2 5v cgnd pgnd v cin pwm disable v in v in r2j20602 reg5v boot v swh v ldrv cgnd pgnd v cc 5v 20k 20k 1f 0.22f 0.22f v in 7v to 14v 470f 4.7f 4.7f 1f 22f 47f s 3 47f s 3 330f s 3 v out1 1.2v 25a 330f s 3 v out2 1.8v 25a 3860 ta02 v in 0.22f 0.3h 0.22f 1f 4.7f 4.7f 22f 4.7k 47pf 1000pf 470pf 0.1f freq set for 600khz 45.3k 100k 49.9k open (opt) 7v to 14v in and 1.2v/1.8v out at 25a f sw = 600khz, dcr sensing ch1 tracks ch2, ch1 uses diffamp note 1: please refer to the r2j20602 data sheet for the most up to date pinout note 2: please refer to the pin configuration of this data sheet for the ltc3860 pinout open (opt) pwm2 v cc 220 v out2 clkout run2 20k 10k 20k 20k 100k 49.9k pwm1 open open (opt) 4.7k 47pf 1000pf run1 0.3h 47 2.74k 2.74k 47 v os1p v os1n
ltc3860 29 3860fc typical applications quad-phase single output with drmos v cc fb1 comp1 vsnsout vsnsn vsnsp comp2 fb2 run1 i lim1 isns1p isns1n isns2n isns2p i lim2 run2 v diff v osn v osp v cc v cc run1 v cc track/ss1 pwm2 track/ss1 vinsns sgnd sgnd i avg pgood1 pwmen1 pwm1 track/ss2 freq clkin clkout phsmd pgood2 pwmen2 pwm2 ltc3860 0.01f 470f 22f 1f v in 7v to 14v v cc 5v run1 v diff track/ss1 100k 49.9k open (opt) open (opt) open (opt) open (opt) open (opt) open (opt) pwm1 pwm3 100pf i avg1 2.2 0.22f sw1 sw2 5v 0.22f 0.22f v cc v cc 47pf 1000pf comp1 470pf 4.7k 220 20k 20k 4.7f 1f v in 2.2 v in 0.22f 5v v cc 22f 4.7f 1f 2k 2k v cc fb1 comp1 vsnsout vsnsn vsnsp comp2 fb2 run1 i lim1 isns1p isns1n isns2n isns2p i lim2 run2 v cc v cc v cc run1 track/ss1 pwm4 track/ss1 vinsns sgnd sgnd i avg pgood1 pwmen1 pwm1 track/ss2 freq clkin clkout phsmd pgood2 pwmen2 pwm2 ltc3860 470f 22f 47f 6.3v s 8 0.4h 0.4h 0.4h 0.4h 1f v in 7v to 14v v cc 5v run1 track/ss1 i avg1 49.9k open (opt) 45.3k open (opt) 2.2 0.22f sw3 sw4 3860 ta03 5v 0.22f 0.22f v cc 4.7f 1f v in 2.2 v in 0.22f 5v 330f 2.5v s 8 v out1 1.2v 100a v cc 22f 4.7f 1f 2k 2k 47 47 v osn v osp v cin disable pwm v in r2j20602 reg5v boot v swh v ldrv cgnd pgnd v cin disable pwm v in r2j20602 reg5v boot v swh v ldrv cgnd pgnd v cin pwm disable v in r2j20602 reg5v boot v swh v ldrv cgnd pgnd v cin pwm disable v in r2j20602 reg5v boot v swh v ldrv cgnd pgnd 4.7f 4.7f 4.7f 4.7f
ltc3860 30 3860fc typical applications dual-phase single output with discrete drivers and mosfets fb1 comp1 vsnsout vsnsn vsnsp comp2 fb2 v diff1 v os1n v os1p v cc v cc i lim1 isns1p isns1n isns2n isns2p i lim2 run2 track/ss2 freq clkin clkout phsmd pgood2 pwm2 v cc track/ss1 vinsns i avg pgood1 pwm1 run1 ltc3860 220pf 1.33k v diff1 v cc v cc 5v 20k 20k 1f pwmen1,2 sgnd 0.22f 0.22f v in 7v to 14v 470f 100pf 0.22f sw1 sw1 0.3h 12.7k 33pf 1.5nf freq set for 600khz 45.3k 7v to 14v in and 1.2v out at 50a f sw = 600khz, dcr sensing pwm2 ss1 clkout run2 0.1f track/ss1 100k 49.9k 2.2 1f 4.7f v cc pwm1 run1 in v logic v cc boost 4 3 2 1 5 6 7 8 4 3 2 1 5 6 7 8 gnd bg ts tg ltc4449 rjk0305dpb v in bg1 tg1 rjk0330dpb rjk0305dpb rjk0330dpb rjk0305dpb rjk0330dpb rjk0305dpb rjk0330dpb 22f s 2 47f s 3 330f s 3 47 v out1 1.2v 50a v os1p v os1n 47 2.74k 2.74k 0.22f sw2 sw2 0.3h 2.2 1f 4.7f v cc in v logic v cc boost gnd bg ts tg ltc4449 v in bg2 tg2 22f s 2 47f s 3 330f s 3 3860 ta04 note: please refer to the pin configuration of this data sheet for the ltc3860 pinout
ltc3860 31 3860fc typical applications dual output3-channel + single channel, synchronized to external clock v cc fb1 comp1 vsnsout vsnsn vsnsp comp2 fb2 run1 i lim1 isns1p isns1n isns2n isns2p i lim2 run2 v diff v osn v osp v cc v cc run1 track/ss1 pwm2 track/ss1 vinsns sgnd sgnd i avg pgood1 pwmen1 pwm1 track/ss2 freq clkin clkout phsmd pgood2 pwmen2 pwm2 ltc3860 0.01f 470f 22f 1f v in 7v to 14v v cc 5v run1 v diff1 clockin 600khz sync input track/ss1 100k 49.9k open (opt) open (opt) open (opt) open (opt) pwm1 i avg1 pwm3 100pf 2.2 0.22f sw1 sw2 5v 0.22f 0.22f v cc v cc 47pf 1000pf comp1 470pf 4.7k 220 20k 20k 47pf 1000pf 470pf 4.7k 220 v diff4 20k 10k 45.3k 4.7f 1f v in 2.2 v in 0.22f 5v v cc 22f 4.7f 1f 2.3k 2.3k v cc fb1 comp1 vsnsout vsnsn vsnsp comp2 fb2 run1 i lim1 isns1p isns1n isns2n isns2p i lim2 run2 v os4p v os4n v cc comp1 pwm4 track/ss1 vinsns sgnd sgnd i avg pgood1 pwmen1 pwm1 track/ss2 freq clkin clkout phsmd pgood2 pwmen2 pwm2 ltc3860 470f 22f 47f 6.3v s 6 0.3h 0.3h 0.3h 0.3h 1f v in 7v to 14v v cc 5v run1 track/ss1 i avg1 49.9k 49.9k open (opt) open (opt) open (opt) 45.3k 100k v cc open (opt) 2.2 0.22f sw3 sw4 3860 ta05 5v 0.22f 0.22f 0.01f run2 v cc 4.7f 1f v in 2.2 v in 0.22f 5v 330f 2.5v s 6 v out1 1.2v 75a v cc 22f 4.7f 1f 2.32k 2.32k 47 v osp 47f s 3 330f s 3 v out4 1.8v 25a 47 v os4p v cin disable pwm v in r2j20602 reg5v boot v swh v ldrv cgnd pgnd v cin disable pwm v in r2j20602 reg5v boot v swh v ldrv cgnd pgnd v cin pwm disable v in r2j20602 reg5v boot v swh v ldrv cgnd pgnd v cin pwm disable v in r2j20602 reg5v boot v swh v ldrv cgnd pgnd 47 v osn 47 v os4n 4.7f 4.7f v cc 4.7f 4.7f
ltc3860 32 3860fc typical applications 2-phase 1.5v/40a converter with delta 20a power blocks and external 400khz clock v cc fb1 comp1 vsnsout vsnsn vsnsp comp2 fb2 run1 i lim1 isns1p isns1n isns2n isns2p i lim2 run2 v diff v osn v osp v cc v cc run1 track/ss1 track/ss1 vinsns sgnd sgnd i avg pgood1 pwmen1 pwm1 track/ss2 freq clkin clkout phsmd pgood2 pwmen2 pwm2 ltc3860 0.1f 470f 1f v in 7v to 14v v cc 5v run1 v diff clockin 400khz sync input track/ss1 100k 59k i avg1 100pf 22f v cc open opt 5v bias 0.22f open opt v cc 100pf 2200pf comp1 470pf 6.8k 523 20k 13.3k 34.8k 10k 22f v in 100f 6.3v 100f 6.3v 3860 ta06 10k 47 47 v osp v osn 0.22f 5v gnd2 pwm temp gnd1 v in enable csp csn v out d12s36a 22f pwm2 pwm1 v cc open opt 5v bias open opt 22f 330f 2.5v s 6 v out 1.5v 40a v in 5v gnd2 pwm temp gnd1 v in enable csp csn v out d12s36a
ltc3860 33 3860fc typical applications dual output converter with emerson 30a (smt30pb-o1sadjj) power blocks fb1 comp1 vsnsout vsnsn vsnsp comp2 fb2 i lim1 isns1p isns1n isns2n isns2p i lim2 run2 v diff1 v os1n v os1p v cc track/ss1 vinsns i avg pgood1 pwm1 run1 track/ss2 freq clkin clkout phsmd pgood2 pwm2 ltc3860 pwmen1,2 sgnd 0.1f 470f 1f 0.1f v in 8v to 14v v cc 5v run1 v diff1 100k 59k pwm1 pwm2 v cc 0.22f v cc 100pf 2200pf 470pf 6.8k 523 20k 29.4k v out2 run2 8v to 14v in and 1.0v/1.8v out at 25a f sw = 400khz ch1 uses diffamp 100pf 2200pf 470pf 6.8k 523 20k 10k 34.8k 100k 59k 100f s 2 3860 ta07 100f s 2 51 51 v os1p v os1n gnd 0.22f 1f v cc open opt 7v bias open opt 22f 330f s 3 gnd 330f s 3 v out1 1v 30a v out2 1.8v 30a v in 7v temp pwm gnd v in v out csp csn 1f v cc open opt open opt 7v bias 22f v in 7v temp pwm gnd v in v out csp csn smt30pb- 01sadjj smt30pb- 01sadjj
ltc3860 34 3860fc package description uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) 5.00 p 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 31 1 2 32 bottom viewexposed pad 3.50 ref (4-sides) 3.45 p 0.10 3.45 p 0.10 0.75 p 0.05 r = 0.115 typ 0.25 p 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 C 0.05 0.70 p 0.05 3.50 ref (4 sides) 4.10 p 0.05 5.50 p 0.05 0.25 p 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 s 45 o chamfer r = 0.05 typ 3.45 p 0.05 3.45 p 0.05
ltc3860 35 3860fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 04/10 updates to features 1 updates to absolute maximum ratings, order information sections, electrical characteristics heading and note 2 2, 3, 4 update to design example section 27 updates to typical applications 30, 31, 33, 35, 38 b 10/10 updated electrical characteristics section 2, 3, 4 updated pin functions 8 updated frequency selection and the phase locked loop (pll) section 12 updated theory and bene? ts of multiphase operation section 13 updated equations 15, 27 updated typical applications 28, 29, 31-33, 36 updated related parts 36 c 03/11 updated v fb and i freq speci? cations in the electrical characteristics section updated pin 10 and pin 28 text in pin functions updated functional diagram updated text in current sharing section updated equation updated related parts 3, 4 8 9 10 23 36
ltc3860 36 3860fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0311 rev c ? printed in usa related parts part number description comments ltc3850/ltc3850-1 ltc3850-2 dual output, 2-phase synchronous step-down dc/dc controller, r sense or dcr current sensing pll fixed 250khz to 780khz frequency, 4v v in 30v, 0.8v v out 5.25v ltc3869/ ltc3869-2 dual output, 2-phase synchronous step-down dc/dc controller with accurate current share pll fixed 250khz to 750khz frequency, 4v v in 38v, v out3 up to 12.5v ltc3856 single output 2-phase synchronous step-down dc/dc controller with diff amp and dcr temperature compensation pll fixed 250khz to 770khz frequency, 4.5v v in 38v, 0.8v v out 5v ltc3855 dual output, 2-phase, synchronous step-down dc/dc controller with diff amp and dcr temperature compensation pll fixed frequency 250khz to 770khz, 4.5v v in 38v, 0.8v v out 12v ltc3775 high frequency synchronous voltage mode step-down dc/dc controller very fast transient response, t on(min) = 30ns, 4v v in 38v, 0.6v v out 0.8v in , msop-16e, 3mm 3mm qfn-16 ltc3853 triple output, multiphase synchronous step-down dc/dc controller, r sense or dcr current sensing and tracking pll fixed 250khz to 750khz frequency, 4v v in 24v, v out3 up to 13.5v ltc4449 high speed synchronous n-channel mosfet driver v in up to 38v, 4v v cc 6.5v adaptive shoot-through protection, 2mm 3mm dfn-8 package ltc4442/ltc4442-1 high speed synchronous n-channel mosfet driver v in up to 38v, 6v v cc 9v adaptive shoot-through protection, msop-8 package ltc3880/ltc3880-1 dual output polyphase step-down dc/dc controller with digital power system management v in up to 24v, 0.5v v out 5.5v, analog control loop, i 2 c/pmbus interface with eeprom and 16-bit adc typical application v cc fb1 comp1 vsnsout vsnsn vsnsp comp2 fb2 run1 i lim1 isns1p isns1n isns2n isns2p i lim2 run2 v diff v osn v osp v cc v cc run1 track/ss1 pwm2 track/ss1 vinsns sgnd sgnd i avg pgood1 pwmen1 pwm1 track/ss2 freq clkin clkout phsmd pgood2 pwmen2 pwm2 ltc3860 0.01f 470f 4.7f 22f 1f v in 7v to 14v v cc 5v run1 v diff1 clockin 600khz sync input track/ss1 100k 59.0k open (opt) open (opt) open (opt) open (opt) pwm1 i avg1 100pf 2.2 0.22f sw1 sw2 5v 100 0.01f 0.01f v cc v cc 47pf 1000pf comp1 470pf 4.7k 220 20k 20k 45.3k 4.7f 1f v in 1m 2.2 v in 0.22f 5v 4.7f v cc 22f 4.7f 1f 47f 6.3v s 4 0.3h 0.3h 330f 2.5v s 4 v out1 1.2v 40a 47 3860 ta08 v osp v cin disable pwm v in r2j20602 reg5v boot v swh v ldrv cgnd pgnd v cin pwm disable v in r2j20602 reg5v boot v swh v ldrv cgnd pgnd 1m 47 v osn dual phase single output with drmos and r sense

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